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Intusoft Newsletter Issue
#37, August 1994
Copyright ©2002
Intusoft, All Rights Reserved
There are a number of ways to
obtain SPICE models, but whether you use models from a pre-made
library, a hardware
vendor, or you make them yourself, you need to be able to maximum,
minimum, and typical versions). In any case, optimizing SPICE
models for any situation, is greatly eased with the new interactive
features of ISSPICE4. Let’s take a look at a modeling example
using the SD5000 Siliconix DMOS MOSFET. The initial model was
developed using the SPICEMOD modeling program that makes SPICE
models from data sheet parameters. As it comes from SPICEMOD,
the model is well within the data sheet tolerances on all key
performance measurements (Figure 1). The threshold
voltage tolerance alone could easily produce the discrepancy in
the initial simulation results. Let’s say we want to exactly
match the typical output curves either provided in the data sheet
or measured in a laboratory. To
accomplish this we can follow these simple steps. Step one:
Build a simple test circuit such as the one shown in Figure
1. Step two: Place the measured data points onto the
simulated waveform in ISSPICE4. This is done with the Points statement
(Figure 1). Any set of data points can be
placed on any real time waveform. Final step: Select the
desired parameters to hand tweak using the interactive stimulus
feature (Stimulus button in the Simulation Control dialog). Adjust
the parameters until the simulated curves align with the data
points (Figure 8).
As the model parameters are changed, the new results will be displayed. With this instant feedback its easy to “dial in” the desired response. The analysis type and simulation limits can be interactively changed, for example, to zoom in on a particular region or optimize the model over multiple domains (freq., DC, time, etc.). ISSPICE4 is the only SPICE program that gives you this level of interactivity. The interactive sweeping may also be used for any subcircuit or for general circuit optimization.
In the past, most signal speeds were slow enough that a connector could be modeled as a simple DC resistance. In today’s high speed RF and microwave environments this is not always the case. The optimum method for generating SPICE models of a connector, and other arbitrarily shaped structures, is with an electromagnetic field solver. The motivations for the connector manufacturer to simulate are clear; connector bandwidth, transit time delay, reflections, crosstalk, and fastest rise/fall times may be established. For the designer, the limitations of physical interconnects and their effects can be thoroughly and accurately explored.
To illustrate the entire modeling and analysis process, Ansoft’s Maxwell©; 3-D Field Simulator was combined with ISSPICE to model both time and frequency domain crosstalk effects of a D-type connector. However, as we will show, other field simulators and connectors could be substituted. In part 1 of this article (June 1994) we entered a D-type connector’s physical representation into the Ansoft Maxwell field simulator. The geometry of the connector included 9 pins, the insulation (e assumed to r be 2) and the metal shell. The solution of the resulting electric and magnetic fields was then used to calculate the connector’s inter-pin capacitances and inductances. Losses come in the form of conductor losses (resistance), dielectric losses (con- ductance), and radiation losses (normally ignored). Most con- nectors are usually short relative to the signal risetime and use low loss materials. Thus, the predominate cause of degradation is model dispersion resulting from the mixed dielectric systems. Therefore, a lossless interconnect model is usually sufficient to accurately represent the connector.
The EM solver results are expressed as a capacitance matrix and an inductance matrix. The leading diagonal of the capaci- tance matrix is the self capacitance of the conductor. It is the sum of the capacitances from the one conductor to all others plus the capacitance of the conductor to ground. Since we solved for the connector in free space, the conductor to ground capacitance is zero. From the 10 x 10 matrix there are 45 capacitances that fully describe the mutual capacitances be- tween the 10 conductors. Figure 2 gives a partial result showing the capacitance from each pin to the shell and to pin 1. The reference for the connector is actually the shell since there can be no voltage induced on the shell. In other connector models the pins may be referenced to some other point, such as a ground plane beneath the connector.
Derivation of the inductance matrix
from the magnetic solution is similar. Within the inductance matrix
the leading diagonal is the self inductance of each conductor.
The matrix is symmetri- cal with the off diagonal terms being
the mutual inductance between conductors m and n. When forming
the SPICE netlist for these inductance terms, it is easier to
convert the self and mutual terms into self inductance plus a
coupling coefficient (SPICE K element) where knm
= sqrt( Mnm/ LnLm). Voltage controlled sources are sometimes
preferred for coupling because of the restriction of keeping the
sign of knm positive. The coupled inductor approach,
however, reduces the number of
nodes to a minimum. The capacitance and inductance matrices were
converted to SPICE subcircuits and used in the inductor/ capacitor
“Tee” network shown in Figure 3.
Virtually all EM solvers output a single subcircuit for each connector
that is compatible with ISSPICE. For simplicity, the inductance
and magnetic cross coupling were split between two arms of the
“Tee” while the capacitance and electrostatic cross
coupling form the vertical limb. The shell is connected to ground.
Once the subcircuit is available,
ISSPICE can then be employed to simulate the connector under a
variety of electrical conditions.
To represent a typical application, we have set the connector
up in an RS232 configuration with pins 2 & 3 as the transmit
and
receive lines terminated at each end in 120 ohms (Figure
3). Pin 2 is driven with an AC signal allowing the designer
to look at the
near end crosstalk on Pin 3. We ran an AC analysis from 100 kHz
to 100MHz. The resulting crosstalk phase and magnitude
waveforms are shown in Figure 4. We can
see that the crosstalk rises at 20dB/decade with a value of -24dB
at 100MHz. At this
frequency, the phase lag is starting to reduce from the lower
frequency 90° lag. A transient analysis could also be run
at different baud rates to look at the effects of crosstalk and
impedance mismatches on the waveform shapes. Twisted pair is usually
used with these connectors so appropriate lossy transmission line
models could be added to represent the lines either side of the
connector.
In a second simulation, we connected
the D connector to the output of a typical IC buffer found in
a PC. For the buffer, we used Intusoft’s IBIS model for the
82430 PCIset of ICs to drive a time domain signal into the connector.
[1] The pin-pin crosstalk
and waveform across the load were also studied under these more
strenuous conditions where the rise/fall times are on the
order of 1-2ns. The schematic and results of the simulation are
shown in Figures 5 and 6.
Note: several new IBIS models for the
82374/5 ICs are included on the newsletter floppy disk.
AC simulations show that this D-Type connector model is useful up to 500MHz where the connector width is approaching a tenth of the wavelength and the lumped parameter model is no longer appropriate. With the “Tee” configuration, the inductance mod- elling is only correct if all the current out of the connector is returned through the connector. This is usually the case where the load end is terminated and the receiver uses a high impedance differential input. Any external return path would require its own self and mutual inductance terms to be calcu- lated. The modeling will remain valid while any external return current is small in comparison to the signal current. This is not always the case for all models, however, the restrictions do result in a simpler model representation.
Next, a more complex model, the CEE Computerbus™ con- nector from Burndy, was simulated in a simple test setup (Figure 7) to measure the connector bandwidth, maximum rise time, and transit time delay. The bandwidth is easily determined from an AC analysis. As shown in Figure 7, the -3db point is at 7.26GHz. The bandwidth is then used to compute the fastest risetime: RT = .35/Bandwidth = .35/7.26GHz ³ 50ps. Thus any signal with a frequency less than 7.26G and rise time slower than 50ps will not be distorted by the connector. A simple pulse waveform was used to check the transit time delay through the connector. It was found to be about 61.65ps (0-5V input), very close to the measured value[3]. Factors affecting the accuracy of this value could be traced to the test setup differences.
Because of the fast rise and fall times many RLCG sections are required to properly model high bandwidths[4]. Connector subcircuits for an entire connector can become very large slowing down the simulation. Therefore, it is best to model only the number of coupled paths necessary to achieve the simula- tion goals. Often only a single pin-pin path with no coupling will suffice. For the simulation in Figure 5, the D connector (³117 elements) took 14.6s on a Pentium/60. The same simulation using the full Computerbus connector model (³2400 elements) took 210.1s. To address this issue AMP offers users of its products several “reduced” models for single connector lines.
While EM solvers support a number of SPICE simulators, some of the features of the Intusoft tools eased the simulation task. ISSPICE can handle very large circuits, so complex connector structures can be simulated. ISSPICE is also very fast, since it is a 32 bit implementation of SPICE. The SPICENET schematic entry package allowed us to draw simple symbols to represent the inductive and capacitive parts of the “Tee” connector model and link them to the ISSPICE subcircuit library. We could then draw the complete connector as 3 simple components without entering any values manually. We have used the waveform calculation facilities within INTUSCOPE to calculate the complex input impedance of connectors against frequency and a number of other parameters not presented here.
In summary, we modeled the capacitive and inductive coupling
in a generic D-type connector using the Maxwell 3D field solver
and have extracted the resulting matrices and SPICE subcircuits.
The same procedures were used for other connectors using precise
figures for dimensions, conductivities and dielectric constants.
The time domain simulations can be extended to look at pulse
distortion effects and ground plane noise. These capabilities
can be used to improve the design of connectors, reduce crosstalk,
and improve impedance matching. It should be noted that EM simulators
are capable of modeling and simulating a variety of objects and
that their SPICE model generation is but one facet of their use.
There are a number of
field solvers on the market, each one capable of performing the
preceding work (See next page). However, as with any software
product, each has different strengths and weaknesses. In a future
article, this work will be extended to model the effects of interconnections
in other parts of the signal path, including the PCB track (microstrip/stripline)
and vias.
As is now common practice for op-amp devices, models are being made available by various connector manufacturers. Several connector models are included on the Intusoft Newsletter floppy from Berg (Micropax surface mount connector (.025" pin spacing)) and Burndy (Computerbus and Microbus .05" cardedge connectors, and ELF low profile surface mount connector). AMP is currently leading the way in support of SPICE connector models. Those interested parties may contact Amp directly. Additional models created by the Ansoft (D type connector), Sonnet (microstrip interconnects) and MSC/EMAS (24 pin right angle connector) EM solver products are also on the enclosed disk for newsletter subscribers.
A maintenance update for the ICAP/4Windows package is NOW AVAILABLE. The update is FREE if downloaded from Intusoft’s CompuServe forum (CAD/CAM/CAE, Go CADDVEN) or $25 (for postage and handling) if ordered from Intusoft. The update is valid for all ICAP/4Windows systems with or without the Deluxe option. You must have the original ICAP/4Windows software in order to install the maintenance update.
The update includes a new version of the Windows Win32s extensions and some new features. One of the most notable is the Copy To Clipboard function for both SPICENET and INTUSCOPE. This function allows you to transport schematics and graphs to your favorite word processor or desk-top publishing program using the Windows meta-file format.
The demand for Intusoft’s NEW low cost simulation solution, ICAP/4Lite, has been tremendous. Many are taking advantage of the special introductory pricing. Until September 15, 1994, ICAP/4Lite is available for the special price of $445. This includes a $150 certificate good towards a variety of ICAP/4Lite upgrades. The upgrade certificate is good until December 15, 1994. For current ICAP/4 owners (Windows, DOS, and Macintosh) the new ICAP/4Lite system is just what you need to supplement your office copy at home. It is priced at $295, a savings of 50% over the regular list price of $595. Price good until 9/15/94. Working demonstration disks are available.
Exact Feature Comparison: A comparison of ICAP/4Lite to other CAE tools is available from Intusoft or your local dealer.
The ICAP/4 Virtual Circuit Design Laboratory is being released
for the entire line of Macintosh computers. Currently, all 68xxx
systems are supported. A special no coprocessor version, ICAP/4MNC,
is now available for the Powerbook series and other Macintosh
computers that do not have a coprocessor. These machines can now
take advantage of the advanced ISSPICE3 (SPICE 3F) features available
in the ICAP/4M package. A native Power Macintosh version of ICAP/4M
will be available early in the fourth quarter. In the mean time,
Power Macintosh users will have access to ICAP/4MNC, the no coprocessor
version. ICAP/4MNC (for Macintosh Powerbooks and Power Macs) is
immediately available for $1575.
n this issue of The Intusoft Modeling Corner we bring you two sample op-amp applications from Maxim and Burr-Brown. The Burr-Brown models add to their current release of over 104 models while this is the first release of Maxim op-amp models.
The low power used by the Maxim op-amps makes it possible to create a simple 2-wire current transmitter that uses no power at the transmitting end except from the transmitted signal itself. At the transmitter, a 0-1V input drives the op-amp and transistor connected as a voltage controlled current sink. The output is sent through a twisted pair or coaxial line to the receiver. The voltage is buffered using another op-amp producing a 0-1V ground referenced signal. Although the supply current is taken from the signal, negligible error (1µA out of 2mA) is sent through the interconnect. The simulation in Figure 9 shows the output for a 0-1V input at V1 and the error (in %) over the range.
The most popular pressure sensors are piezoresistive bridges that produce a differential output whose voltages are generally 25 to 75mV full scale. In order to interface devices such as these to a microprocessor, the output must be scaled into an appropriate range for A to D conversion and converted from a differential to a single ended signal. The circuit in Figure 10 accomplishes this with the absolute pressure sensor connected to a Burr-Brown instrumentation amp (INA114) in a basic transducer amplifier setup. ISSPICE can be used to study the effects of power supply, gain, and sensor changes. Feedback from a control system to the sensor input may also be employed. In this case, note how the constant gain changes under low pressure inputs. Pressure, and other sensors, are part of the standard ICAP/4 libraries.
On the Intusoft Newsletter floppy disk for subscribers, we have enclosed several connector models plus 18 models for Maxim low power op-amps and 12 models for Burr-Brown devices. Maxim specializes in micropower, ultra low noise op-amps. New models for the MAX402 family (High-speed micropower), MAX406 family (1.2uA IDD, 2.5V-10V supply, 10pA Ib) and MAX410 family (Low-noise) are available. Models for 5 other families are due out shortly. See the next Intusoft Newsletter for more details or contact MAXIM INTEGRATED PRODUCTS - Applications Engineering 120 San Gabriel Dr. Sunnyvale, CA. USA 94086, 408/737-7600. Several photodiode, DMOS, and IBIS models, created by Intusoft Tech support are also included on the floppy. The IBIS models are for various buffers in the 82374 and 82375 set of Intel ICs.
Stimulating Circuits With Behavioral Models
When digital data must be transmitted over a band limited channel, it must first be coded onto a carrier using amplitude, frequency, or phase modulation. Creation of generators for such signals can greatly simplify the study of communication systems. Shown in Figure 11 are the ISSPICE subcircuits for phase-shift keying and frequency-shift keying sources.
Coherent Binary PSK Source
The subcircuit PSK produces a coherent binary PSK signalaccording
to the following equations;
s1(t) = sqrt(2 Eb / Tb) * sin(2 þ f t)
s2(t) = -sqrt(2 Eb / Tb) * sin(2 þ f t)
where Eb is the transmitted energy per bit, Tb is the bit duration, and f is the transmission frequency. The frequency, f, is chosen to be Nc/Tb. The input voltage source VSIG produces the polar form of the input signal. This input is then multiplied by the local oscillator voltage VLO1 to produce the PSK output signal.
Coherent Binary FSK Source
The subcircuit FSK produces a coherent binary FSK signal according
to the following equations;
s1(t) = sqrt(2 Eb / Tb) * sin(2 þ f1 t)
s2(t) = sqrt(2 Eb / Tb) * sin(2 þ f2 t)
where f1 is the high bit transmission frequency and f2 is the low bit transmission frequency. The frequency, f1, is chosen to be Nc+1/Tb. The frequency, f2, is chosen to be Nc+2/Tb. For simplicity, two pulse generators are used to produce the input signal (m(t)) and the inverse of the message signal (M(t)).
These signals are multiplied by the appropriate frequency generator (VFO1 for logic high and VFO2 for logic low). The resultant signals are summed to produce the FSK output signal.
Copyright ©2002 Intusoft, All Rights Reserved
